1. Field of the Invention
The present invention relates to a low level clamp circuit for clamping a low level of a multilevel clock signal having, for example, at least three levels. More specifically, this invention relates to a low level clamp circuit suitably used for clamping a low level of a multilevel clock signal in which an intermediate level, in particular, is required to be stabilized, for instance when the multilevel clock signal is used as an image element driving clock for a charge-coupled device (CCD).
2. Description of the Prior Art
As a driving clock for a vertical register for solid image elements such as a so-called CCD imager, a three-level clock signal as shown in FIG. 1 is used. Where a clamping operation is used to stabilize the levels of this three-level clock signal, a low-level clamping operation is preferable to maintain the stability of the clamping operation, since the clamping period is short. In general, when an electric charge of the CCD image elements is transferred, the second (intermediate) level of a multi-level driving clock is very important. Therefore, it has been especially desirable to improve the accuracy of the second level of the driving clock signal.
When a three-level clock signal as shown in FIG. 1 is clamped at its lowest level and then supplied to the CCD image element, there exist drawbacks in that the amplitude in the driving clock signal changes between the low level and the second (intermediate) level due to power supply voltage fluctuations or element characteristic fluctuations based upon temperature change. Thus, the clamped second level fluctuates while transferring the electric charge relative to the stable low level. An example of a prior art low level clamp circuit will be described as to circuit configuration and operation under the section captioned.